Processor structure and method for maintaining and restoring precise state at any instruction boundary
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 15, 1997
Issued Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Feb 14, 1995
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring precise state at any instruction boundary; (3) tracking instruction status to maintain precise state; (4) checkpointing instructions to maintain precise state; (5) creating, maintaining, and using a time-out checkpoint; (6) tracking floating-point exceptions; (7) creating, maintaining, and using a watchpoint for plural, simultaneous, unresolved-branch evaluation; and (9) increasing processor throughput while maintaining precise state.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully