Methods for controlling timing in a logic emulation system
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Jul 15, 1997
Issued Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Jan 31, 1992
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A method and a structure for implementing integrated circuit designs into a plurality of clocked and unclocked reprogrammable logic circuits. Software structures analyze the target logic circuit, form clusters, partitions the integrated circuit design and implement the partitions into the clocked and unclocked reprogrammable logic circuits in order to prevent hold time violation artifacts.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully