Importance

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Abstract

In a VRAM having a flash write function, paired bit lines in a memory cell array are divided into first paired bit lines on the side of memory cells and a pre-charge equalizing circuit, and second paired bit lines on the side of paired column selecting transfer gates, by paired bit line transfer gates. One end of first and second flash write MOS transistors is connected to bit lines of the second paired bit lines. The other ends are set at a bit line pre-charge potential or a predetermined reference potential by a potential changeover circuit. With the potential changeover circuit, not only the original flash write function but also a bit line equalizing function can be carried out. Thus, it is possible to pre-charge bit lines sufficiently in a short period of time even when the power source potential is low, and to sense data read from memory cells with precision.

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First Claim