Semiconductor read-only VLSI memory
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United States of America Patent
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Jul 22, 1997
Issued Date -
N/A
app pub date -
Sep 6, 1996
filing date -
May 5, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
The performance of a very large scale integrated READ ONLY MEMORY circuit is improved by a number of different improvements in various circuits and methodologies utilized in the memory. One of the improvements relates to control of an output buffer by a control circuit. The output enable signal to the output buffer is selectively inhibited by the control circuit which determines when the memory cycle is actually completed. Only after the memory cycle is actually completed is the conventional chip enable signal, CE, coupled to the enable input in the output buffer.
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