Layered polysilicon deposition method

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United States of America Patent

PATENT NO 5652156
SERIAL NO

08419050

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A method of forming a multilayered polysilicon gate which inhibits penetration of ions through the polysilicon gate to the underlying gate oxide layer is described. A gate silicon oxide layer is formed over the surface of a semiconductor substrate. A layer of amorphous silicon is grown overlying the gate silicon oxide layer. A layer of polysilicon is grown over the amorphous silicon layer wherein silicon grain boundaries of the polysilicon layer are misaligned with silicon grain boundaries of the amorphous silicon layer. The amorphous silicon and the polysilicon layers are etched away where they are not covered by a mask to form the multilayered polysilicon gate. The mismatched silicon grain boundaries of the multilayered polysilicon gate inhibit ions from penetrating through the polysilicon gate to the underlying gate oxide layer.

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Patent Owner(s)

  • TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Jiaw-Ren, Shih Hsin-Chu, TW 1 36
Liao, Siu-han Hsin-Chu, TW 8 144

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