Apparatus for performing wafer-level testing of integrated circuits where the wafer uses a segmented conductive top-layer bus structure
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United States of America Patent
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Aug 5, 1997
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app pub date -
Jun 7, 1995
filing date -
Jul 23, 1993
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Abstract
Wafer level testing of a wafer (500) is accomplished by dividing the integrated circuits of the wafer into a plurality of segmented bus regions (514, 516, and 518 for example). Each bus region is formed having its own set of test conductors (520-530) wherein each set of test conductors are isolated from all other sets of test conductors on the wafer. Each test conductor has at least one contact pad (531-546) where each contact pad lies within a periphery of the integrated circuits' active areas. By forming pads over ICs and by sub-dividing the bus structure of test conductive lines, more high powered ICs can be tested in a wafer-level manner with fewer problems associated with speed, power, throughput, and routing problems.
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