Timing-driven integrated circuit layout through device sizing
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United States of America Patent
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Aug 5, 1997
Issued Date -
N/A
app pub date -
Jul 11, 1995
filing date -
May 10, 1993
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method and apparatus for determining the layout of an integrated circuit, in accordance with timing constraints, by means of sizing the buffers in the layout. A nominal netlist for the layout of the integrated circuit is used to determine critical paths through the circuit. The time-critical paths are determined and the instances of the buffers along the path are resized so that the time delays in the time-critical paths are either brought within the predetermined timing criteria, or no further improvement in any time-critical path is possible.
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