DMA controller having a plurality of DMA channels each having multiple register sets storing different information controlling respective data transfer
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United States of America Patent
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Aug 5, 1997
Grant Date -
N/A
app pub date -
Jan 28, 1994
filing date -
Jan 28, 1994
priority date (Note) -
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Abstract
A direct memory access (DMA) controller is connected with the CPU bus of a computer system through a bus interface and also to an I/O bus, which is connectable to one or more I/O controllers. The DMA controller contains multiple channels, each corresponding to a particular I/O controller, which are coupled to both the bus interface and the I/O bus. Each of the channels contains at least one register set storing information for the transfer and a data buffer holding the data during a transfer between the I/O bus and the CPU bus.
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