Clock synthesizer dual function pin system and method therefor
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United States of America Patent
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Aug 12, 1997
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N/A
app pub date -
Nov 24, 1995
filing date -
Nov 24, 1995
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Abstract
An improved clock synthesizer system and method therefor is described which uses a plurality of dual function pins to apply a frequency selection code while in a first operating mode and to transmit buffered clock signal while in a second operating mode to accomplish required system functions with a reduced overall pin count.
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