Clock distribution network for reducing clock skew
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United States of America Patent
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Aug 12, 1997
Grant Date -
N/A
app pub date -
Sep 8, 1995
filing date -
Sep 8, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A clock distribution network for distributing a clock signal across a VLSI chip. A H-tree is combined with an x-y grid to allow buffering of the clock signal, while minimizing clock skew across the chip. The H-tree distributes a plurality of repower buffer levels above a final repower buffering level. The output of the final level are coupled by the x-y grid to minimizes clock skew caused by the chip and by local loading variations in the circuits.
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