Importance

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Abstract

A method and apparatus for eliminating bus contention among multiple drivers in a computer system by synchronizing the output enables of all of the respective drivers within the system to the system bus clock. This synchronization eliminates the variation between the output enables across the system and thus ensures that there is no difference between the best case output enable time and the worst case output disable time. In this manner, the potential for bus contention between drivers is eliminated. In the preferred embodiment of the invention various methods may be used to synchronize a respective device's output enables to the system bus clock. The logic device which actually generates the system bus clock preferably uses a clock correlation method which matches various delays within the device to synchronize the output enables throughout the device. Other devices preferably use either digital phase locked loop (PLL) methods or digital delay correlation methods to synchronize their respective output enables. Digital delay correlation involves delay chain logic which generates an early clocking signal referred to as pCLK that is asserted a certain number of delays prior to the CLK signal rising edge. This early clocking signal is used to synchronize the output enables of the device to the CLK signal rising edge.

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First Claim