Device for controlling memory data path in parallel processing computer system
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United States of America Patent
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Aug 19, 1997
Issued Date -
N/A
app pub date -
Apr 18, 1996
filing date -
Nov 30, 1995
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Abstract
A memory data path controller for a large-scale parallel processing computer system in which, when a network interface and bus interface request access to a single-port memory, a dual path controller dividedly stores memory access requests in network queue and bus queue. This allows a single-port DRAM to be used as a dual-port memory device. Further, the network queue and bus queue are multi-staged to store sequential memory requests and transmit reading/writing data of the network queue or bus queue to the DRAM memory.
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