Importance

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Abstract

In order to delay, as far as possible, the time at which the interrupt request at the newest highest priority level is determined and to shorten the response time for an interrupt request with a high priority level, a microprocessor has control circuit 15, when an interrupt request is received, for inputting an interrupt priority level value obtained from a group of interrupt request signals IPL0# to IPL2 # simultaneously with the input of an interrupt vector for an interrupt request from a plurality of data buses D0 to D15, setting this interrupt level value in a mask register 13 as the mask level when the interrupt process is executed; and controlling a mask circuit 11 for masking an interrupt request of an interrupt priority level the same as or lower than an interrupt priority request level received during the execution of the interrupt process.

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First Claim