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Abstract

A computer system includes a single-chip central processor (20) with handshaking and direct memory access (DMA) controllers for accommodating first and second types of DMA to a dynamic random access memory (DRAM) (34). The single-chip central processor (20) has a kernel processor (22) having cache, a memory management and control unit (26), and a coprocessor (24). The computer system further includes a bundle of lines (28), including data lines, address lines and row address strobe (RAS), column address strobe (CAS), output enable (OE), and write enable (WE) lines for coupling the memory management and control unit (26) to the DRAM (34), and a plurality of data exchanges (33, 37) coupled to a plurality of first and second attach controllers (32, 36). The coprocessor includes a plurality of DMA controllers (240-246) for storing addresses and for storing a length representing a number of data items to be transferred. Additionally, each DMA controller is coupled by a separate line (303) to a respective first attach controller for accommodating a first type of DMA, between the memory and the plurality of data exchanges, which generates addresses of contiguous memory. The plurality of second attach controllers accommodates a second type of DMA between the memory and the plurality of data exchanges. The coprocessor further includes a plurality of handshake controllers (250-256), each for executing handshaking with a respective second attach controller, not under control of the kernel processor.

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First Claim