Internal timing method and circuit for programmable memories
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United States of America Patent
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Sep 2, 1997
Grant Date -
N/A
app pub date -
Feb 21, 1995
filing date -
Feb 18, 1994
priority date (Note) -
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Abstract
A circuit generates flexible timing permitting a slow or fast overall timing configuration, and two configurations of the precharge and detecting intervals by providing both with two (short or long) duration levels. For this purpose, the circuit includes a variable, asymmetrical propagation line composed of a succession of elementary delay elements enabled or disabled on the basis of memorized logic signals, the state of which is determined when debugging the memory in which the circuit is implemented.
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