Apparatus and method for testing a memory array
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United States of America Patent
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Sep 2, 1997
Grant Date -
N/A
app pub date -
Oct 6, 1995
filing date -
Oct 6, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
There is disclosed a central controller for simultaneously testing the embedded arrays in a processor. Test data vectors are serially shifted into a latch and stored into each location in the embedded arrays of the processor. The test data are then read out of the embedded arrays into a read latch and serially shifted into a multiple input shift register, where a polynomial division is performed on the test vector data. If all memory locations in the embedded array function properly, a remainder value will result that is equal to a unique signature remainder for the test vectors used.
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