Importance

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Abstract

A digital filter for image processing which permits a reduction in the size of the circuit includes a plurality of bit shifters for multiplying each picture element data of a k.times.k matrix, each by a coefficient which corresponds to the respective picture element. A first adder circuit adds the output data of all of the bit shifters. A first multiplier circuit multiplies picture element data of a center picture element of the k.times.k matrix by a predetermined coefficient. A second multiplier circuit multiplies output data of the first adder circuit by a predetermined coefficient and a second adder circuit adds output data of the first multiplier circuit and that of the second multiplier circuit.

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First Claim