Importance

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Abstract

A data cache array which includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing at least a portion of an address for that block of information and a data status field for providing an indication of data validity within that cache line. An allocation control cell is associated with each cache line and a pseudo least recently utilized (PLRU) logic circuit is provided within the data cache array for each group of cache lines. The pseudo least recently utilized (PLRU) logic circuit is then utilized to select and set a particular allocation control cell within each group of cache lines in response to utilization of those cache lines. The cache line allocation process is then utilized to select a particular cache line within a group of cache lines for replacement in response to either an indication of invalidity of the block of information within that cache line or in response to the state of the pseudo least recently utilized (PLRU) logic circuit for that group of cache lines, if the block of information within every cache line within the group is indicated as valid.

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First Claim