Display refresh system having reduced memory bandwidth
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United States of America Patent
Stats
-
Sep 23, 1997
Grant Date -
N/A
app pub date -
Jun 7, 1995
filing date -
Jun 7, 1995
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A display refresh system (10) is disclosed wherein a display image is stored in a screen memory (12) as a number of screen rows (26) having consecutive addressable units. A redundancy memory (38) includes a redundancy row (48) corresponding to each screen row (26). Each redundancy row (48) stores run length data that indicates the number of identical consecutive addressable units within a screen row (26). Addressable units are written with accompanying run lengths to a FIFO (54). A register repeater (56) repeats the addressable unit at the FIFO output (62) a number of times equal to the run length. The run length is used to advance the refresh address to the next group of identical consecutive addressable units within the screen row (26).
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