Method and apparatus for performing write operations in multi-level cell storage device

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United States of America Patent

PATENT NO 5671388
SERIAL NO

08433614

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Abstract

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A memory contains a plurality of memory cells that are capable of storing one or more bits of data in each memory cell. The memory stores, in response to a write operation, data corresponding to the write operation in a first set of the memory cells such that each cell of the first set of the memory cells stores a single bit. Thereafter, data from the first set of memory cells are transferred to a second set of the memory cells such that each cell of the second set of the memory cells stores more than a single bit of data. The write operation to the first set of cells is executed in a foreground operation, and in a subsequent background operation, data from the first set of memory cells are transferred to the second set of memory cells. The memory cells are non-volatile flash electrically erasable programmable read only memory (EEPROM) cells, and therefore require erasure before programming. Typically, memory cells are reclaimed in a background operation. However, if not enough memory cells are available for a write operation, then a set of memory cells are reclaimed in a foreground operation, and more than one bit of the data are stored in the reclaimed memory cells.

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Patent Owner(s)

Patent OwnerAddress
INTEL CORPORATION2200 MISSION COLLEGE BOULEVARD SANTA CLARA CA 95054

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Hasbun, Robert N Shingle Springs, CA 55 3531

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