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Abstract

A method for interconnecting and operating in parallel a number of autonomous data processors each having a data memory, an instruction memory and a communication interface includes, before beginning a data processing sequence, loading memories of the autonomous data processors with individual algorithms, data sets and protocol instructions. A hardware communication system common to all of the autonomous data processors is connected to communicate with the communication interfaces of all of the data processors to regulate operation of the data processors. The communication system is programmed with an overriding body of execution sequence commands for the data processors to initiate and sequence autonomous processing of data in the data processors. The communication system communicates commands to initiate processing of the loaded data sets in accordance with the loaded algorithms in the data processors, independently of each other, to individually arrive at processing results and make the results available to the communication system, and the communication system reads and communicates the processing results.

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First Claim