Semiconductor integrated circuit for processing image data

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5673422
SERIAL NO

08376618

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A frame buffer memory includes a main memory of a DRAM, a cache memory of a SRAM, a first transfer bus for transferring data of 256 bits, for example, between the main memory and the cache memory, a pixel processing unit for carrying out a predetermined operational process according to data provided from the cache memory and externally applied data, a compare unit for comparing the data provided from the cache memory with externally applied data, a transfer bus for transferring data from the cache memory to the pixel processing unit and the compare unit, a transfer bus for transferring resultant data from the pixel processing unit to the cache memory, and a serial access memory for storing data read out from the main memory and providing the stored data serially to an outside world. According to the structure, an .alpha.-blend process, a raster operation, a Z compare process and the like required for graphics can be carried out at high speed with flexibility.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
RENESAS ELECTRONICS CORPORATIONTOKYO 135-0061

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Inoue, Yoshitsugu Hyogo, JP 36 413
Kawai, Hiroyuki Hyogo, JP 160 1909
Nakamura, Hisashi Hyogo, JP 80 1088

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation