Semiconductor integrated circuit for processing image data
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United States of America Patent
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Sep 30, 1997
Grant Date -
N/A
app pub date -
Jan 23, 1995
filing date -
Jan 21, 1994
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Abstract
A frame buffer memory includes a main memory of a DRAM, a cache memory of a SRAM, a first transfer bus for transferring data of 256 bits, for example, between the main memory and the cache memory, a pixel processing unit for carrying out a predetermined operational process according to data provided from the cache memory and externally applied data, a compare unit for comparing the data provided from the cache memory with externally applied data, a transfer bus for transferring data from the cache memory to the pixel processing unit and the compare unit, a transfer bus for transferring resultant data from the pixel processing unit to the cache memory, and a serial access memory for storing data read out from the main memory and providing the stored data serially to an outside world. According to the structure, an .alpha.-blend process, a raster operation, a Z compare process and the like required for graphics can be carried out at high speed with flexibility.
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Patent Owner(s)
| Patent Owner | Address | |
|---|---|---|
| RENESAS ELECTRONICS CORPORATION | TOKYO 135-0061 |
International Classification(s)
Inventor(s)
| Inventor Name | Address | # of filed Patents | Total Citations |
|---|---|---|---|
| Inoue, Yoshitsugu | Hyogo, JP | 36 | 413 |
| Kawai, Hiroyuki | Hyogo, JP | 160 | 1909 |
| Nakamura, Hisashi | Hyogo, JP | 80 | 1088 |
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| Surcharge after expiration - Late payment is unavoidable | $700.00 | $350.00 | $175.00 |
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