Fast carry-out scheme in a field programmable gate array
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United States of America Patent
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Oct 7, 1997
Grant Date -
N/A
app pub date -
Oct 26, 1995
filing date -
Oct 26, 1995
priority date (Note) -
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status (Latency Note)
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Abstract
A fast carry-out scheme in a field programmable logic array. The configurable logic blocks (CLBs) are arranged in columns. The carry-out signals are routed from the bottom CLB of a column to the top CLB of that column. The carry-out from the top-most CLB is then multiplexed onto a clock line that is normally used to conduct clocking signals to the CLBs. Instead of conducting clocking signals, the existing clock line is now used to route the carry-out signal onto a vertical longline spanning the entire height of the column. Eventually, the carry-out signal is routed from the longline to its destination CLB of the adjacent column via local interconnect resources.
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