A/D reference level adjustment circuit to maintain optimum dynamic range at the A/D
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United States of America Patent
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Oct 7, 1997
Grant Date -
N/A
app pub date -
Jul 31, 1995
filing date -
Jul 31, 1995
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method and circuit for controlling a reference voltage for an analog-to-digital converter having plural outputs includes a sensor for indicating when outputs from the A/D converter are at least a desired voltage, and a processor responsive to the sensor and connected to a digital-to-analog converter which provides a reference voltage for the A/D converter. The processor provides signals to the D/A converter which change the reference voltage. A logic unit in the processor increments an accumulator when either an I or a Q component in the A/D converter output is at least the desired voltage and decrements the accumulator when neither the I nor the Q component is at least the desired voltage. A counter may buffer the accumulator changes by using only several of the most significant bits of the counter to change the A/D converter reference voltage.
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