Method to derive the functionality of a digital circuit from its mask layout
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United States of America Patent
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Oct 14, 1997
Grant Date -
N/A
app pub date -
Nov 3, 1995
filing date -
Nov 3, 1995
priority date (Note) -
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Abstract
A method for generating a simplified model of a complex binary transistor circuit. A set of Boolean functions are derived for the circuit and these functions are tested to determine if the circuit is stable and binary. All intermediate transient circuit configurations are eliminated so that only direct transitions between stable circuit configurations remain. If the circuit is also combinational, a logic circuit is generated. If the circuit is not combinational but if there is a clock input to the circuit that controls the values of the node (the circuit exhibits synchronous behavior) and all nodes in the circuit are well-defined (either combinational or level-sensitive), a logic circuit is generated. The logic circuit is processed to generate a further simplified logic circuit by merging different types of latches and other logic elements and removing duplicative logic elements.
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