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Abstract

In a semiconductor memory device constituted by bulk CMOS 6-Tr memory cells, a structure is realized which can maintain a high soft error immunity even if a power-supply voltage is lowered and a cell size is decreased. In order to realize this structure, a semiconductor memory device using a flip-flop which is constituted by CMOS transistors formed on a surface of a semiconductor substrate, includes a trench isolating region which has an interface between a first conductive well and a second conductive well formed in the semiconductor substrate and is formed from the surface of the semiconductor substrate in a direction of depth to have a predetermined planar shape and a predetermined depth, and a trench capacitor formed in the trench isolating region and separately connected to two memory nodes of a memory cell.

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First Claim