Importance

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Abstract

An interrupt vector approach for a processor system loads an interrupt vector directly into an address. register to minimize overhead of processing interrupts. A plurality of interrupt triggers correspond to a plurality of interrupt vector registers, each containing a programmable interrupt vector. Upon activation of one of the interrupt triggers, the contents of the corresponding interrupt vector is loaded into a slot memory address counter. The address counter addresses a sequencer slot memory which contains the starting addresses of sequences of instructions stored in an instruction memory. An instruction address counter receives addresses from the sequencer slot memory and provides addresses to the instruction memory. Upon activation of said one of the interrupt triggers, execution of one of the sequences beginning at the address contained in the interrupt register corresponding to the active interrupt trigger is begun, and addresses of the sequences in sequencer slot memory are sequentially loaded into the instruction address counter until a stop bit is indicated in a word in the sequencer slot memory.

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First Claim