Multi-processor data processing system with multiple, separate instruction and operand second level caches
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United States of America Patent
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Oct 21, 1997
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N/A
app pub date -
Dec 28, 1995
filing date -
Dec 28, 1995
priority date (Note) -
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Abstract
A multiprocessor data processing system having store-through first-level caches with separate instruction and operand sections and a store-in second-level cache that is shared between the processors and which has separate instruction and operand sections. Dual second-level caches, each mappable to all of shared memory, enhance cache performance. The second-level cache memory space is divided into a plurality of segments, with each segment having a dedicated instruction tag memory, a dedicated operand tag memory, a dedicated instruction cache memory, and a dedicated operand cache memory. The segments may be addressed in parallel to further enhance cache performance.
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