FPGA architecture with repeatable tiles including routing matrices and logic matrices
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United States of America Patent
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Oct 28, 1997
Grant Date -
N/A
app pub date -
Mar 19, 1996
filing date -
Apr 1, 1994
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
An FPGA architecture offers logic elements with direct connection to neighboring logic elements and indirect connection through a routing matrix. A logic element and a portion of the routing matrix are formed as part of a tile, and tiles are joined to form arrays of selectable size. The routing matrix includes routing lines which connect just from one tile to the next and routing lines which extend longer distances through several tiles or through the entire chip. This combination is achieved by the formation of individual tiles, all of which are identical.
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