High speed three-state sampling
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United States of America Patent
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Oct 28, 1997
Grant Date -
N/A
app pub date -
Apr 13, 1995
filing date -
Apr 13, 1995
priority date (Note) -
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Abstract
The present invention describes a novel method and apparatus for sampling an input/output pin of an electronic device at high speeds, comprising the steps of: driving the device input/output pin through a series resistor with a middle voltage between the high and low voltages of the device; sampling and latching the voltage at the input/output pin; comparing the latched voltage at the device input/output pin with a high threshold voltage which is between the high voltage of the device and the middle voltage; comparing the latched voltage at the device input/output pin with a low threshold voltage which is between the low voltage of the device and the middle voltage; and using the results of the two comparisons to determine whether the device input/output pin is driving high, driving low, or in an input mode.
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