CAS recognition in burst extended data out DRAM
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United States of America Patent
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Oct 28, 1997
Grant Date -
N/A
app pub date -
Nov 6, 1995
filing date -
Nov 6, 1995
priority date (Note) -
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Importance
Abstract
An integrated memory circuit is described which can be operated in a burst access mode. The memory circuit includes an address counter which changes column addresses in one of a number of predetermined patterns. The memory includes generator circuit for generating an internal control signal based upon external column address signals. The generator circuit detects the first active transition of the column address signals and the first inactive transition of the column address signals.
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