Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier
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United States of America Patent
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Oct 28, 1997
Grant Date -
N/A
app pub date -
Dec 29, 1994
filing date -
Dec 29, 1994
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
An array processor topology reconfiguration system and method enables processor elements in an array to dynamically reconfigure their mutual interconnection for the exchange of arithmetic results between the processors. Each processor element includes an interconnection switch which is controlled by an instruction decoder in the processor. Instructions are broadcast to all of the processors in the array. The instructions are uniquely interpreted at each respective processor in the array, depending upon the processor identity. The interpretation of the commonly broadcast instruction is uniquely performed at each processor by combining the processor identity for the executing processor, with a value in the instruction. The resulting control signals from the instruction decoder to the interconnection switch, provides for a customized linkage between the executing processor and other processors in the array.
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