Importance

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Abstract

A memory controller for controlling access to a memory array from a microprocessor and a plurality of devices is described. The memory controller also allows access between the microprocessor and the plurality of devices. The memory controller interfaces the microprocessor and the plurality of devices. The memory controller comprises an interface circuit coupled to the microprocessor and the plurality of devices to receive an access request from one of the microprocessor and the plurality of devices for determining whether the access request is a memory access request for the memory array. A memory control circuit is coupled to the interface circuit for controlling access to the memory array when the access request is the memory access request. A refresh control circuit is coupled to the memory control circuit and the interface circuit for causing the memory control circuit to refresh the memory array when the access request received in the interface circuit is a non-memory access request such that the memory array is refreshed concurrently with handling of the non-memory access request by the interface circuit. A method of causing the memory controller to concurrently refresh the memory array is also described.

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First Claim