Use of deferred bus access for address translation in a shared memory clustered computer system
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United States of America Patent
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Oct 28, 1997
Grant Date -
N/A
app pub date -
Jun 30, 1995
filing date -
Jun 30, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
In a shared memory computer system, processing nodes are coupled together by way of cluster bridges. A cluster bridge operating according to the present invention intercepts a global access transaction request issued from a processing node and issues a transaction deferral to indicate that the request will be serviced out-of-order. A map of global addresses which correspond to fixed addresses at the node from which the access request was issued is maintained by the cluster bridge. If the address of the global access transaction request corresponds to a fixed address local to the requesting node, the address is translated at cluster bridge and accessed at the local node in order to complete the deferred request.
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