FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions
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United States of America Patent
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Nov 4, 1997
Grant Date -
N/A
app pub date -
Jul 23, 1996
filing date -
Jul 29, 1992
priority date (Note) -
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status (Latency Note)
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Abstract
An array of FPGAs change their configurations successively during performance of successive user-defined algorithms. Adjacent FPGAs are connected through external field programmable interconnection devices (FPINs) or cross-bar switches. The array includes a processor-like device capable of performing the computations necessary to reconfigure the FPGAs in the array in accordance with the next algorithm to be performed. Preferably, this processor-like device is itself a 'control' array of interconnected FPGAs which have been configured to emulate a selected microprocessor architecture which accepts user-defined primitives corresponding to an algorithm to be performed or a logic architecture to be emulated and reconfigure the FPGAs and the FPINs accordingly.
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