Importance

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Abstract

In accordance with this invention, a synchronization circuit generates a synchronized signal and a synchronized clock from an input signal and a clock signal. The synchronization circuit is insensitive to the clock signal prior to and during a predetermined time period after the occurrence of a leading edge in the synchronized signal, thus avoiding the metastable problem. The synchronized signal has a leading edge derived from a leading edge in the input signal and a trailing edge in synchronization with a trailing edge in the synchronized clock. The synchronized clock has a leading edge derived from a leading edge in the clock signal and a trailing edge derived from a trailing edge in the clock signal. One embodiment of a synchronization circuit is used in a host adapter integrated circuit which buffers data between a system bus and an input/output bus. The system bus clock signal is supplied as the input signal and the host adapter's clock signal is supplied as the clock signal to the synchronization circuit. The synchronized signal and the synchronized clock are then used to drive a data FIFO queue in the host adapter.

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First Claim