Local punchthrough stop for ultra large scale integration devices

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5686321
SERIAL NO

08647266

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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The invention relates to an improved MOSFET device structure for use in ultra large scale integration and the method of forming the device structure. A local punchthrough stop region is formed directly under the gate electrode using ion implantation. The local punchthrough stop region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local punchthrough stop region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. The source and drain junction capacitances are also reduced. The invention can be used in either N channel or P channel MOSFET devices. The invention can be used with a conventional source/drain structure as well as a double doped drain structure and a light doped drain structure.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
UNITED MICROELECTRONICS CORP.HSINCHU3834

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ko, Joe Hsin-Chu, TW 43 870
Lin, Chih-Hung I-Lain, TW 95 567

Cited Art Landscape

Patent Info (Count) # Cites Year
 
NXP B.V. (1)
* 5399508 Method for self-aligned punchthrough implant using an etch-back gate 19 1993
 
BRIGHT MICROELECTRONICS INCORPORATED (1)
* 5364806 Method of making a self-aligned dual-bit split gate (DSG) flash EEPROM cell 72 1993
 
UNITED MICROELECTRONICS CORP. (2)
* 5413949 Method of making self-aligned MOSFET 50 1994
* 5538913 Process for fabricating MOS transistors having full-overlap lightly-doped drain structure 76 1995
 
MOTOROLA, INC. (1)
* 5372960 Method of fabricating an insulated gate semiconductor device 28 1994
 
LG Semicon Co., Ltd. (2)
* 5374574 Method for the fabrication of transistor 19 1993
* 5374575 Method for fabricating MOS transistor 69 1993
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
ADVANCED MICRO DEVICES, INC. (1)
* 6216099 Test system and methodology to improve stacked NAND gate based critical path performance and reliability 13 1997
 
ROUND ROCK RESEARCH, LLC (2)
* 6156632 Method of forming polycide structures 4 1997
6355549 Method of forming polycide structures 1 2000
 
POLARIS INNOVATIONS LIMITED (1)
6458664 Method for fabricating a field-effect transistor having an anti-punch-through implantation region 1 2000
 
NEC CORPORATION (1)
* 6077747 Method of manufacturing semiconductor device 4 1998
 
CHARTERED SEMICONDUCTOR MANUFACTURING PTE. LTD. (1)
* 5856225 Creation of a self-aligned, ion implanted channel region, after source and drain formation 175 1997
 
POWERCHIP SEMICONDUCTOR CORP. (1)
* 5963811 Method of fabricating a MOS device with a localized punchthrough stopper 13 1997
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (1)
* 6232160 Method of delta-channel in deep sub-micron process 6 1999
 
Semiconductor Energy Laboratory Co., Ltd. (3)
* 6897526 Semiconductor device and process for producing the same 12 1999
7687855 Semiconductor device having impurity region 1 2005
* 2005/0156,209 Semiconductor device and process for producing the same 0 2005
 
GLOBALFOUNDRIES INC. (1)
* 6355528 Method to form narrow structure using double-damascene process 9 1999
 
SEIKO INSTRUMENTS INC. (1)
* 2007/0205,466 Semiconductor device 2 2007
 
AURIGA INNOVATIONS, INC. (1)
* 6159807 Self-aligned dynamic threshold CMOS device 11 1998
 
ALTERA CORPORATION (2)
* 6417550 High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage 15 1997
6972234 High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage 5 2000
 
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. (4)
6410394 Method for forming self-aligned channel implants using a gate poly reverse mask 10 1999
6297132 Process to control the lateral doping profile of an implanted channel region 98 2000
6204137 Method to form transistors and local interconnects using a silicon nitride dummy gate technique 24 2000
6489191 Method for forming self-aligned channel implants using a gate poly reverse mask 4 2002
* Cited By Examiner