US Patent No: 5,686,321

Number of patents in Portfolio can not be more than 2000

Local punchthrough stop for ultra large scale integration devices

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Abstract

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The invention relates to an improved MOSFET device structure for use in ultra large scale integration and the method of forming the device structure. A local punchthrough stop region is formed directly under the gate electrode using ion implantation. The local punchthrough stop region reduces the expansion of the depletion region in the channel and thereby increases the punchthrough voltage. The local punchthrough stop region is self-aligned with the gate electrode and source/drain region so that critical spacings are maintained even for sub micron devices. The source and drain junction capacitances are also reduced. The invention can be used in either N channel or P channel MOSFET devices. The invention can be used with a conventional source/drain structure as well as a double doped drain structure and a light doped drain structure.

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Patent Owner(s)

Patent OwnerAddressTotal Patents
UNITED MICROELECTRONICS CORP.HSINCHU4351

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ko, Joe Hsin-Chu, TW 43 813
Lin, Chih-Hung Gueiren Township, Tainan County, TW 108 425

Cited Art Landscape

Patent Info (Count) # Cites Year
 
LG SEMICON CO., LTD. (2)
5,374,574 Method for the fabrication of transistor 19 1993
5,374,575 Method for fabricating MOS transistor 69 1993
 
UNITED MICROELECTRONICS CORP. (2)
5,413,949 Method of making self-aligned MOSFET 46 1994
5,538,913 Process for fabricating MOS transistors having full-overlap lightly-doped drain structure 75 1995
 
MOTOROLA, INC. (1)
5,372,960 Method of fabricating an insulated gate semiconductor device 26 1994
 
NXP B.V. (1)
5,399,508 Method for self-aligned punchthrough implant using an etch-back gate 19 1993
 
WINBOND ELECTRONICS CORP. (1)
5,364,806 Method of making a self-aligned dual-bit split gate (DSG) flash EEPROM cell 72 1993

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
CHARTERED SEMICONDUCTOR MANUFACTURING LTD. (5)
5,856,225 Creation of a self-aligned, ion implanted channel region, after source and drain formation 159 1997
6,410,394 Method for forming self-aligned channel implants using a gate poly reverse mask 9 1999
6,297,132 Process to control the lateral doping profile of an implanted channel region 43 2000
6,204,137 Method to form transistors and local interconnects using a silicon nitride dummy gate technique 21 2000
6,489,191 Method for forming self-aligned channel implants using a gate poly reverse mask 2 2002
 
ALTERA CORPORATION (2)
6,417,550 High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage 11 1997
6,972,234 High voltage MOS devices with high gated-diode breakdown voltage and punch-through voltage 5 2000
 
ROUND ROCK RESEARCH, LLC (2)
6,156,632 Method of forming polycide structures 4 1997
6,355,549 Method of forming polycide structures 0 2000
 
SEMICONDUCTOR ENERGY LABORATORY CO., LTD. (2)
6,897,526 Semiconductor device and process for producing the same 11 1999
7,687,855 Semiconductor device having impurity region 0 2005
 
ADVANCED MICRO DEVICES, INC. (1)
6,216,099 Test system and methodology to improve stacked NAND gate based critical path performance and reliability 12 1997
 
GLOBALFOUNDRIES INC. (1)
6,355,528 Method to form narrow structure using double-damascene process 8 1999
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (1)
6,159,807 Self-aligned dynamic threshold CMOS device 11 1998
 
NEC CORPORATION (1)
6,077,747 Method of manufacturing semiconductor device 4 1998
 
POWERCHIP SEMICONDUCTOR CORP. (1)
5,963,811 Method of fabricating a MOS device with a localized punchthrough stopper 6 1997
 
QIMONDA AG (1)
6,458,664 Method for fabricating a field-effect transistor having an anti-punch-through implantation region 0 2000
 
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (1)
6,232,160 Method of delta-channel in deep sub-micron process 5 1999