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Abstract

The circuit for clock signal extraction from a high speed data stream which allows a rapid attainment of the identity between the frequencies of the locally generated clock signal and of the data signal, even when such frequencies are very different. The circuit can easily be inserted into a more complex CMOS digital integrated circuit, it has low power dissipation and is capable of operating at bit rates exceeding 300 Mbit/s. The circuit has a main phase locked loop, which controls a voltage controlled oscillator by continually controlling its phase and a secondary loop, which allows the main loop to become locked, by causing the voltage controlled oscillator to oscillate at a frequency close to the operating frequency.

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First Claim