Importance

Loading Importance Indicators...

Abstract

A monolithic CMOS phase-lock loop (PLL) circuit provides a high frequency of operation suitable for RF applications. The PLL produces an output clock with high spectral purity and very low jitter. The output clock has a low static phase error relative to a reference input, making the PLL useful for clock synchronizing applications, such as clock recovery elements in transmission/recording channels. The PLL provides in-phase and quadrature signals from a voltage controlled oscillator (VCO) which has two differential transconductors. The second differential transconductor has a positive input coupled to a positive output of the first differential transconductor, a negative input coupled to a negative output of the first differential transconductor, a positive output coupled to a negative input of the first differential transconductor, and a negative output coupled to a positive input of the first differential transconductor. Each differential transconductor has a negative output impedance. Each differential transconductor includes a current controlled transconductor circuit (CCXG) and a voltage-current converter coupled to a first supply node for providing a current to the CCXG responsive to a voltage applied to a voltage control input of the differential transconductor.

Loading the Abstract Image...

First Claim