Low voltage one transistor flash eeprom cell using fowler-nordheim programming and erase
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United States of America Patent
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Nov 11, 1997
Grant Date -
N/A
app pub date -
Sep 27, 1995
filing date -
Mar 3, 1994
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A single transistor electrically erasable programmable memory device capable of being programmed and erased using Fowler-Nordheim tunneling and capable of being operated using low voltages. Portions of each of the source and drain regions overlap with the first gate dielectric layer, and the interpoly dielectric layer is chosen to have a high dielectric constant so as to maximize the capacitive coupling ratio between floating gate, control gate, source, and drain. The logical condition of cells in the array is set by first elevating a block of cells to a high voltage threshold and by individually lowering the voltage threshold of selected cells.
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