Multiple-bank memory architecture and systems and methods using the same
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
Nov 11, 1997
Grant Date -
N/A
app pub date -
Oct 26, 1995
filing date -
Oct 26, 1995
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A memory 20 is disclosed including a first column of memory cells including a conductive bitline 202 and a second column of memory cells also including a conductive bitline 202. A gate 203 is provided for selectively coupling the bitline 202 of the first column with the bitline 202 of the second column for transferring a bit of data from a selected cell of the first column to a selected cell of the second column.
First Claim
Family
International Classification(s)
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully