3D stack of IC chips having leads reached by vias through passivation covering access plane
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United States of America Patent
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Nov 18, 1997
Grant Date -
N/A
app pub date -
Mar 26, 1996
filing date -
Mar 15, 1994
priority date (Note) -
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Abstract
A process in which a plurality of IC chips are stacked in a unitary structure having a novel method of exposing leads on the access plane of the stack. After a layer of dielectric material has been formed on the access plane, trenches (preferably trenches) are formed, e.g., by wet lithographic processing, which expose the access plane leads. Thereafter terminals are formed on the access plane in contact with the leads. At the wafer level, layers of dielectric material are deposited which are sufficiently thick to permit the subsequent forming of trenches in the access plane dielectric without uncovering any of the silicon of the IC chips.
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