Multi-chip device and method of fabrication employing leads over and under processes
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United States of America Patent
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Nov 18, 1997
Grant Date -
N/A
app pub date -
Dec 19, 1995
filing date -
Dec 19, 1995
priority date (Note) -
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status (Latency Note)
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Abstract
A device and method for increasing integrated circuit density comprising a pair of superimposed dies with a plurality of leads extending between the dies. The device is produced by providing a lower die which has a plurality of bond pads on a face side of the lower die. A layer of dielectric or insulative shielding is applied over the lower die face side. Leads are applied to an upper surface of the shielding layer. A plurality of lower die bond wires is attached between the lower die bond pads and an upper surface of their respective leads. A second layer of dielectric or insulative shielding is applied over the leads and the portion of the lower die bond wires extending over the lead upper surfaces. A back side of the upper die is adhered to an upper surface of the second shielding layer. A plurality of upper die bond wires are attached between a plurality of bond pads on a face side of the upper die and the upper surface of their respective leads.
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