Method for forming studs and interconnects in a multi-layered semiconductor device
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United States of America Patent
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Nov 18, 1997
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N/A
app pub date -
Dec 18, 1996
filing date -
Oct 14, 1994
priority date (Note) -
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Abstract
A method of manufacturing a semiconductor device having a stud and interconnect in a dual damascene structure uses selective deposition. The method includes forming a trench including a first opening portion and a second opening portion in a dielectric layer, forming a first adhesion layer on a surface exposed by the first opening portion, forming a second adhesion layer on a surface exposed by the second opening portion, and selectively depositing a conductive material on the first adhesion layer and the second adhesion layer, wherein growth of the conductive material on the second adhesion layer starts after growth of the conductive material on the first adhesion layer has started. The first and second adhesion layers are of different materials.
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