Importance

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Abstract

A circuit and method for optimizing efficiency in transferring a block of data having a plurality of frames of limited size from a memory element. The circuit comprises a transmit ('TX') DMA engine and a TX Segmentation engine. The TX DMA engine is responsible for accessing overhead information for the block of data within a TX data buffer from a data descriptor dedicated to that particular TX data buffer. The TX DMA engine is further responsible for reading the block of data from the memory element to be stored local thereto. The TX Segmentation engine is responsible for segmenting the block of data into a plurality of cell packets corresponding in number to the plurality of frames. Each cell packet contains in common the overhead information for the block of data to avoid the TX DMA engine re-accessing the data descriptor to obtain the same overhead information for each frame being transferred.

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First Claim