Parallel computing system with processing element number setting mode and shortest route determination with matrix size information

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United States of America Patent

PATENT NO 5689647
SERIAL NO

08551694

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Abstract

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A parallel computer system includes a plurality of processing elements each including a network control unit and a data processing unit. The network control unit of each processing element includes a north, east, west and south ports to each of which a row and column communication lines are connected so as to construct a torus mesh network. A specific mode flag which is set by a reset signal from a host computer coupled to the network and a number register are formed in the data processing unit. If a packet is sent to the network from the host computer when the specific mode flag is set, in the processing element which received the packet, the processing element number included in the packet is set in the number register and the specific mode flag is reset so that the processing element can be identified by that processing element number in a normal mode. In the normal mode, the packet is inputted to the data processing unit when the processing element number of the packet is coincident with its own processing element number. If not coincident, the packet is outputted to a port determined by a predetermined algorithm so that the packet can be transferred to an addressed processing element on the network with the shortest distance.

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Patent Owner(s)

  • SANYO ELECTRIC CO., LTD.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Miura, Hiroki Osaka-fu, JP 60 1182

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