Data transferring system with multiple port bus connecting the low speed data storage unit and the high speed data storage unit and the method for transferring data

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 5689670
SERIAL NO

08671106

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Abstract

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A data processing system using a prefetch mechanism with high speed cache memory to increase the processing speed. Data is prefetched from a low speed main memory to the cache memory for data transfer instructions via multiple ports. For a program control transfer instruction, the prefetch mechanism prefetches instruction for each possible program path, stores them in the cache memory and continues with the prefetch processes.

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International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Luk, Fong 2926 Lambeth Ct., San Jose, CA 95132 9 57

Cited Art Landscape

Patent Info (Count) # Cites Year
 
Other [Check patent profile for assignment information] (1)
* 5051068 Compressors for vehicle tires 24 1990
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (3)
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* 4679141 Pageable branch history table 80 1985
* 4825357 I/O controller for multiple disparate serial memories with a cache 18 1987
 
HEWLETT-PACKARD COMPANY (1)
* 4724518 Odd/even storage in cache memory 37 1987
 
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. (1)
* 5038278 Cache with at least two fill rates 22 1990
 
MICRON TECHNOLOGY, INC. (1)
* 4439827 Dual fetch microsequencer 47 1981
 
XEROX CORPORATION (1)
* 4843542 Virtual memory cache for use in multi-processing systems 107 1986
 
MOTOROLA, INC. (1)
* 4701844 Dual cache for independent prefetch and execution units 90 1986
 
INTERGRAPH HARDWARE TECHNOLOGIES COMPANY (1)
* 4860192 Quadword boundary cache system 82 1986
 
DUKE UNIVERSITY (1)
* 5050068 Method and apparatus for using extracted program flow information to prepare for execution multiple instruction streams 59 1988
 
NEC CORPORATION (2)
* 4881170 Instruction prefetch control apparatus 41 1987
* 4984154 Instruction prefetching device with prediction of a branch destination address 78 1988
 
INTEL CORPORATION (1)
* 4594659 Method and apparatus for prefetching instructions for a central execution pipeline unit 61 1982
 
Storage Computer Corporation (1)
* 5257367 Data storage system with asynchronous host operating system communication link 189 1990
 
SCHLUMBERGER TECHNOLOGY CORPORATION (1)
* 4755935 Prefetch memory system having next-instruction buffer which stores target tracks of jumps prior to CPU access of instruction 36 1986
 
MITSUBISHI DENKI KABUSHIKI KAISHA (2)
* 4847753 Pipelined computer 45 1987
* 4974154 Computer with instruction prefetch queue retreat unit 39 1987
 
STORAGE TECHNOLOGY CORPORATION (1)
* 4476526 Cache buffered memory subsystem 160 1981
 
COMPUTERVISION CORPORATION (2)
* 4860197 Branch cache system with instruction boundary determination independent of parcel boundary 84 1987
* 4894772 Method and apparatus for qualifying branch cache entries 68 1987
* Cited By Examiner

Patent Citation Ranking

Forward Cite Landscape

Patent Info (Count) # Cites Year
 
INTERNATIONAL BUSINESS MACHINES CORPORATION (2)
* 5961654 Operand fetch bandwidth analysis 12 1996
6499116 Performance of data stream touch events 37 1999
 
ROCKWELL COLLINS, INC. (4)
6320284 Motor assembly allowing output in multiple degrees of freedom 20 1999
6664666 Motor assembly allowing output in multiple degrees of freedom 21 2001
6909205 Motor assembly allowing output in multiple degrees of freedom 22 2003
* 2004/0124,717 Motor assembly allowing output in multiple degrees of freedom 2 2003
 
Marvell Israel (M.I.S.L) Ltd. (1)
8938585 Transparent processing core and L2 cache connection 0 2014
 
CISCO SYSTEMS ISRAEL LTD. (2)
* 7027446 Method and apparatus for set intersection rule matching 6 2001
* 2003/0018,693 Method and apparatus for set intersection rule matching 3 2001
 
MARVELL ISRAEL (MISL) LTD. (2)
8688911 Transparent processing core and L2 cache connection 0 2009
* 8484421 Cache pre-fetch architecture and method 0 2009
 
ORACLE AMERICA, INC. (1)
* 6237066 Supporting multiple outstanding requests to multiple targets in a pipelined memory system 16 1999
 
CANON KABUSHIKI KAISHA (2)
* 9030713 Data processing apparatus and data processing method 0 2011
* 2012/0026,540 DATA PROCESSING APPARATUS AND DATA PROCESSING METHOD 1 2011
* Cited By Examiner