Data transferring system with multiple port bus connecting the low speed data storage unit and the high speed data storage unit and the method for transferring data

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United States of America Patent

PATENT NO 5689670
SERIAL NO

08671106

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Abstract

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A data processing system using a prefetch mechanism with high speed cache memory to increase the processing speed. Data is prefetched from a low speed main memory to the cache memory for data transfer instructions via multiple ports. For a program control transfer instruction, the prefetch mechanism prefetches instruction for each possible program path, stores them in the cache memory and continues with the prefetch processes.

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Luk, Fong 2926 Lambeth Ct., San Jose, CA 95132 9 61

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