Cache memory system and method for accessing a coincident cache with a bit-sliced architecture
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United States of America Patent
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Nov 18, 1997
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N/A
app pub date -
Jul 15, 1993
filing date -
Jul 15, 1993
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Abstract
A 'bit-sliced' construction cache module dictates dual TAG RAM Structures and dual invalidation queues, yielding enhanced performance: putting half the TAG array in each of two cache arrays, and allowing each to handle only one-half of the possible address values. Preferably, one half-module handles ZERO least-significant bits and the other handles ONE least-significant bits. Processor operations and invalidation operations can be 'overlapped', and even operate simultaneously.
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