Method of manufacturing BICMOS integrated circuits
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United States of America Patent
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Nov 25, 1997
Grant Date -
N/A
app pub date -
Jun 25, 1996
filing date -
Jun 30, 1995
priority date (Note) -
Expired
status (Latency Note)
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Abstract
A method of manufacturing both bipolar and CMOS devices including vertical PNP, NPN, PMOS and NMOS devices on the same chip, includes the steps of, simultaneously forming an N+ region (14) on part of a P base region (11) of the vertical NPN device to form the emitter contact region thereof, an N+ region (14) on a part of an N- epitaxial layer (5) of the vertical NPN device to form the collector contact region thereof, N+ regions (14) on first and second parts of a P well region (8) of the NMOS device to form the source and drain thereof, and an N+ region (14) on an N base region (9) of the vertical PNP device to form the base contact thereof. In a further simultaneous step, there are formed P+ regions (15) on the P-well (8) and N base (9) regions of the vertical PNP device to form the collector and emitter contact regions thereof, P+ regions (15) on first and second parts of the N- epitaxial layer (5) of the PMOS device to form the source and drain thereof, and a P+ region (15) on part of the P base region (11) of the vertical NPN device to form the base contact region thereof.
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