Recovery unit for mirrored processors
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United States of America Patent
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-
Nov 25, 1997
Grant Date -
N/A
app pub date -
Apr 30, 1996
filing date -
Apr 14, 1995
priority date (Note) -
Expired
status (Latency Note)
Importance
Abstract
A method for making a processor system immune to circuit failure caused by external noise using mirrored processors, and a recovery unit integral with the method, are disclosed. Identical addresses and data information is generated in each of two processors. The data is then partitioned into registers and Error Correction Codes (ECC's) are generated for the data. The address, data, and ECC information for each processor is then interlaced in a data structure. The interlaced structures of each processor are then compared. If the comparison yields no errors, the data is checkpointed in the recovery unit; if an error is detected, a recovery sequence can be initiated after the check-stop operation, whereby the system is restored to the last error-free checkpointing operation.
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